D/A conversion apparatus and A/D conversion apparatus

ABSTRACT

It purposes to provide a D/A conversion apparatus of a high accuracy oversampling method by noise shaping which is not needed a high frequency clock or accurate working, and a high accuracy A/D conversion apparatus having a configuration to which said D/A conversion technology is applied. It has configuration outputting the digital signal by dividing to plural 1-bit D/A converters, and by using said D/A converters so as to circulate, correlation of the signal and the output value of a specified 1-bit D/A converter is canceled, and noise or distortion due to a relative error of the 1-bit D/A converter is reduced.

FIELD OF THE INVENTION

The present invention relates to a D/A (digital/analog) conversionapparatus for converting a digital signal to an analog signal, and anA/D (analog/digital) conversion apparatus for converting the analogsignal to the digital signal, and particularly relates to a D/Aconversion apparatus and an A/D conversion apparatus of oversamplingtype for performing D/A conversion, A/D conversion with a samplingfrequency which is higher than a sampling frequency of the digitalsignal.

BACKGROUND OF THE INVENTION

As one of a D/A conversion apparatus, a D/A conversion apparatus using anoise shaper and a PWM is reported. The D/A conversion apparatus of thismethod which have been reported hitherto is elucidated by using FIG. 24.Incidentally, this technology is described in "National Technical Report(Volume 34, No. 2, April 1988) pp. 40-45", for example.

FIG. 24 is a block diagram showing an example of a conventional D/Aconversion apparatus. Numeral 10 designates a digital filter (DF), andwhich multiplies a sampling frequency fs of an inputted digital signalby k (k≧2). Herein, it is set to k=64. Numeral 11 designates the noiseshaper (NS), and word length limitation of the digital signal which isoutput from the DF 10 is performed, and frequency characteristic ofnoise is changed to a predetermined characteristic thereby. Herein, itis provided that a noise shaper of third order characteristic is usedand an output Y with respect to an input X is represented by an equation(1):

    Y=X+(1-z.sup.-1).sup.3 ·Vq                        (1)

where,

Vq: quantizing error,

z⁻¹ =cos θ-j. sin θ,

j: imaginary number unit.

Moreover, it is provided that the output Y has an output of 11 level(=p). Numeral 19 designates a pulse width modulation circuit (PWM=pulsewidth modulator), and which converts to a pulse signal of 1-bit having11 ways of pulse width corresponding to the digital signal output fromthe NS 11, and outputs as an analog signal. The D/A conversion apparatusof FIG. 24 further converts to the analog signal by using a clock of atleast 704 times (=64×11) by the PWM 19, after a digital input signal ismade to 64 fs of sampling frequency and 11 levels by the DF 10 and theNS 11, and is a D/A conversion apparatus of so called oversampling typefor converting the digital signal to an analog signal with a highersampling frequency.

Further detailed configuration of the NS 11 of FIG. 24 is shown in FIG.25. Numeral 50 designates a first order ΔΣ modulator (1st orderdelta-sigma modulator) which outputs by performing quantization of theinput X and change of the frequency characteristic of the noise andextracts a quantizing error component -Vq1 and outputs to a next step.An output Y1 with respect to the input X is represented by an equation(2):

    Y1=X+(1-z.sup.-1)·Vq1                             (2)

where,

Vq1: quantizing error.

Moreover, it is here assumed that the output Y1 has outputs (-3-+3) ofseven levels (=p1). Numeral 51 designates a second order ΔΣ modulator,and the quantizing error component -Vq1 of the first order ΔΣ modulator50 and performs quantization of the above-mentioned input -Vq1 andoutputs change of the frequency characteristic of the noise. An outputY2 with respect to the input -Vq1 is represented by an equation (3):

    Y2=Vq1+(1-z.sup.-1).sup.2 ·Vq2                    (3),

where,

Vq2: quantizing error.

Moreover, it is here assumed that the output Y2 has outputs (-1, 0, +1)of 3 levels. Numeral 52 designates a differentiator, and the output Y2is digital-differentiated and is output. An output Y2' with respect tothe input Y2 of the differentiator 52 is represented by an equation (4):##EQU1##

The output Y2' at this time has outputs (-2-+2) of 5 levels (=p2).Numeral 53 designates an adder, and the output Y of the NS 11 isobtained by adding the outputs Y1 and Y2'.

In the D/A conversion apparatus of FIG. 24, result derived by simulationon output signal spectrum in the case of 64 fs of sampling frequency(FS), about 0.02 fs of input signal frequency and 0 dB of the inputsignal level is shown in FIG. 26. For simplicity, a signal until 0-2 fsis shown here. As mentioned above, although a digital signal of only 11levels is converted into an analog signal, as shown in FIG. 26, adynamic range (D.R.) of 120 dB or more is obtained in a signal band of0-fs/2 by the NS 11.

However, in the configuration shown in FIG. 24, the PWM 19 requires aclock frequency of at least 704 fs. For example, in the case of asampling frequency fs=48 kHz which is widely used in a digital audio, itbecomes extremely high clock frequency such as 704 fs=33.792 MHz, andthere is a problem in actual use so that countermeasure toelectro-magnetic interference or electro-magnetic disturbance isrequired.

In the case that the D/A conversion is performed by a method except forthe PWM, operation by a clock which is lower than the case of the PWM ispossible. For example, a D/A conversion circuit using a resistor arrayis usable. However, extremely high relative-accuracy is required in theresistor array for this purpose. The reason is that the digital signalwhich is limited in word length by the NS 11 maintains a high accuracyof 120 dB or more in the original signal band (0-fs/2) in spite of alittle word length as mentioned above. Namely, the accuracy of the D/Aconversion is decided by the accuracy of the resistor array. And thereis such a problem that fabrication of the D/A conversion circuit becomesdifficult because the resistor array of the high accuracy is required inorder to the D/A conversion of the high accuracy.

By the way, an A/D conversion apparatus of over-sampling type based on asimilar concept have been reported. The higherto reported A/D conversionapparatus of this method is elucidated by using FIG. 27. This technologyis described in "Institute of Electronics, Information and CommunicationEngineers Technical Report CS83-198".

FIG. 27 is a block diagram showing an example of the conventional A/Dconversion apparatus. Referring to FIG. 27, numeral 70 designates asubtracter which outputs a difference of two analog signals inputtedthereto. An analog input from outside is inputted to an addition addingterminal of the subtracter 70. Numeral 71 designates an integrator, andan analog signal output from the subtracter 70 is output byaccumulating. Numeral 72 designates a quantizer, and which makes adigital output by converting the analog signal output from theintegrator 71 to the digital signal. It is here assumed thatquantization of 2 bits (p=4 ways) is performed, and correspondencebetween input and output is shown in Table 1. Here, it is assumed thatthe analog input is signals of ±1.

                  TABLE 1                                                         ______________________________________                                        Input value of Output value of                                                quantizer 72   quantizer 72                                                   ______________________________________                                        +1.0 . . . +∞                                                                          +1.5                                                            0.0 . . . +1.0                                                                              +0.5                                                           -1.0 . . . 0.0 -0.5                                                            -∞ . . . -1.0                                                                         -1.5                                                           ______________________________________                                    

Numeral 79 designates a D/A converter, which converts the output of thequantizer 72 to an analog signal. The output of the D/A converter 79 isinputted to a subtraction terminal of the subtracter 70.

The A/D conversion apparatus of FIG. 27 is known as the A/D converter ofa noise shaping type of first order characteristic, and the output Ywith respect to the input X is represented by an equation (5):

    Y=X+(1-z.sup.-1)·Vq                               (5),

where,

Vq: quantizing error of quantizer 72, z⁻¹ =cos θ-j·sin θ,

j: imaginary number unit.

In the A/D conversion apparatus of FIG. 27, result derived by simulationon output signal spectrum in the case of 64 fs of sampling frequency(FS), about 0.02 fs of input signal frequency and 0 dB of input signallevel is shown in FIG. 28. For simplicity, a band until 0-2 fs is shownhere. As shown in FIG. 28, a dynamic range (D.R.) of about 57 dB isobtained in the signal band of 0-fs/2.

However, in the configuration shown in FIG. 27, it is considered thatthe D/A converter 79 requires an accuracy of at least the order of thedigital signal to be obtained. For example, the case in which the outputof the D/A converter 79 has 3% of error as shown in Table 2 is presumed.

                  TABLE 2                                                         ______________________________________                                        Input value of D/A                                                                           Output value of D/A                                            converter 79   converter 79                                                   ______________________________________                                        +1.5           1.50                                                           +0.5           0.50                                                           -0.5           -0.48                                                          -1.5           -1.50                                                          ______________________________________                                    

Result derivewd by simulation on output signal spectrum in this case isshown in FIG. 29. For simplicity, a band until 0-2 fs is shown here. Asshown in FIG. 29, generation of large harmonic distortion is observed,and the dynamic range is seriously deteriorated to about 45 dB in thesignal band of 0-fs/2.

This cause is that the output of the D/A converter 79 has nonlinearcharacteristic. Therefore, in order to obtain a high dynamic range,there is a subject in which a device of high accuracy has to be used forthe D/A converter 79.

SUMMARY OF THE INVENTION

The present invention is for resolving the above-mentioned conventionalsubject and purposes to provide a D/A conversion apparatus which doesnot require a high clock frequency such as a PWM and moreover does notrequire a high accuracy in the D/A conversion circuit, and to provide anA/D conversion apparatus which does not require a device of a highaccuracy for the D/A converter 79.

In order to achieve this purpose, the present invention is configuratedas below-mentioned. Namely, (1) it comprises a digital filter formultiplying sampling frequency of an inputted digital signal by k (k≧2),a noise shaper to which the output of the above-mentioned digital filteris inputted and a frequency characteristic of noise is changed to apredetermined characteristic with word length limitation, a decoder towhich the output of the above-mentioned noise shaper is inputted and forconverting to 1-bit signal array corresponding to the value of theabove-mentioned input, 1-bit D/A converter array which is comprised ofplural 1-bit D/A converters for converting the output of theabove-mentioned decoder to an analog signal and an analog adder fortotalizing the outputs of the above-mentioned 1-bit D/A converter array;and it is made a D/A conversion apparatus in which the output of theabove-mentioned decoder is made to an output so that 1-bit signals ofthe number corresponding to the output value of the above-mentionednoise shaper circulate.

Moreover, the present invention, (2) comprises the digital filter formultiplying the sampling frequency of the inputted digital signal by k(k≧2), a noise shaper of a multi step quantization type to which theoutput of the above-mentioned digital filter is inputted and forchanging frequency characteristic of noise to a predeterminedcharacteristic with word length limitation, plural number of decoder towhich outputs of the respective steps of the above-mentioned noiseshaper are inputted and for converting to 1-bit signal arraycorresponding to the values of the above-mentioned inputs, 1-bit D/Aconverter array which is comprised of plural number of 1-bit D/Aconverter for converting the respective outputs of the above-mentioneddecoder to analog signals and an analog adder for totalizing the outputsof the above-mentioned 1-bit D/A converter array; and it is made a D/Aconversion apparatus in which the output of the above-mentioned decoderis made to an output so that the 1-bit signals of the numbercorresponding to the value of the output of the above-mentioned noiseshaper circulate.

Moreover, the present invention, (3) comprises a subtracter to which twoanalog signals are inputted and outputs a difference of both, anintegrator for integrating an analog output of the above-mentionedsubtracter, a quantizer for converting the output of the above-mentionedintegrator to a digital signal, a decoder for converting the digitaloutput of the above-mentioned quantizer to a 1-bit signal arraycorresponding to the value of the above-mentioned signal, a 1-bit D/Aconverter array for converting the output of the above-mentioned decoderto the analog signal, respectively and an analog adder for totalizingthe outputs of the above-mentioned 1-bit D/A converter array and outputto the subtraction terminal of the above-mentioned subtracter; and it ismade an A/D conversion apparatus in which the analog input is inputtedto the addition terminal of the above-mentioned subtracter, the digitaloutput is output from the above-mentioned quantizer and the outputs ofthe above-mentioned decoder is made to an output so that the 1-bitsignals of the number corresponding to the value of the output of theabove-mentioned quantizer circulate.

Moreover, the present invention, (4) comprises a first subtracter towhich two analog signals are inputted and a difference of both isoutput, a first integrator for integrating the analog output of theabove-mentioned first subtracter, a second subtracter to which theanalog output of the above-mentioned first integrator is inputted to theaddition terminal, a second integrator for integrating the analog outputof the above-mentioned second subtracter, a quantizer for converting theoutput of said second integrator to a digital signal, a decoder forconverting the digital output of the above-mentioned quantizer to a1-bit signal array corresponding to the value of the above-mentionedsignal, a 1-bit D/A converter array for converting the output of theabove-mentioned decoder to the analog signals, respectively and ananalog adder for totalizing the outputs of the above-mentioned 1-bit D/Aconverter array and for outputting to the subtraction terminals of theabove-mentioned first and second subtracters; and it is made an A/Dconversion apparatus in which analog input is inputted to the additionterminal of the above-mentioned first subtracter, the digital output isoutput from the above-mentioned quantizer, and the output of theabove-mentioned decoder is made to an output so that the 1-bit signalsof the number corresponding to the value of the output of theabove-mentioned quantizer circulate.

By the above-mentioned configuration, the present invention is that thesampling frequency in the D/A conversion may be identical with thesampling frequency of the digital output of the noise shaper, andoperation in a clock frequency which is far lower in comparison with thePWM is capable by converting the output of the noise shaper in the D/Aconverter to the 1-bit signal array by the decoder and by converting tothe analog signal by the 1-bit D/A converter array. Moreover,correlation between the output value of the noise shaper and aparticular 1-bit D/A converter is canceled by the decoder's allotting ofthe output of the noise shaper to the plural number of 1-bit D/Aconverter so as to circulate. By this, even in the case that a relativeerror (dispersion) is included in the output between the respective1-bit D/A converters, generation of distortion and noise in the signalband may be reduced.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram representing an embodiment of the D/Aconversion apparatus in accordance with the present invention, FIG. 2 isa circuitry representing an example of the D/A conversion circuit 15 ofFIG. 1, FIG. 3 is a block diagram representing an example of a decoder12 of FIG. 1, FIG. 4 is an output signal spectrum of the D/A conversionapparatus of FIG. 1, FIG. 5 is an output signal spectrum in the casethat the output of a pointer 30 does not depend on an input and is fixedto 0 in the D/A conversion apparatus of FIG. 1, FIG. 6 is an outputsignal spectrum in the case that operation of the pointer 30 does notdepend on the output of an NS 11 and is made to output repeatedly thesignals of 0-9 in turn in the D/A conversion apparatus of FIG. 1, FIG. 7is an output signal spectrum of the D/A conversion apparatus of FIG. 1based on Table 6, FIG. 8 is a block diagram representing otherembodiment of the D/A conversion apparatus in accordance with thepresent invention, FIG. 9 is a block diagram representing an embodimentof a noise shaper 41 of FIG. 8, FIG. 10 is a circuitry representing anexample of a D/A conversion circuit 47 of FIG. 8, FIG. 11 is an outputsignal spectrum of the D/A conversion apparatus of FIG. 8 based on Table9, FIG. 12 is an output signal spectrum of the D/A conversion apparatusof FIG. 8 based on Table 10, FIG. 13 is an output signal spectrum of theD/A conversion apparatus of FIG. 8 based on Table 11, FIG. 14 is anoutput signal spectrum of the D/A conversion apparatus of FIG. 8 basedon Table 12, FIG. 15 is a block diagram representing an embodiment ofthe A/D conversion apparatus in accordance with the present invention,FIG. 16 is a circuitry representing an example of a D/A conversioncircuit 73 of FIG. 15, FIG. 17 is an output signal spectrum of the A/Dconversion apparatus of FIG. 15, FIG. 18 is an output signal spectrum inthe case that operation of the pointer 30 does not depend on the outputof the NS 11 and is made to output repeatedly the signals of 0-9 in turnin the A/D conversion apparatus of FIG. 15, FIG. 19 is a block diagramrepresenting other embodiment of the A/D conversion apparatus inaccordance with the present invention, FIG. 20 is a spectrum of anoutput signal of the A/D converter of FIG. 19, FIG. 21 is an outputsignal spectrum of the A/D conversion apparatus of FIG. 19 based onTable 2, FIG. 22 is an output signal spectrum of the A/D conversionapparatus of FIG. 19 based on Table 15, FIG. 23 is an output signalspectrum in the case that operation of the pointer 30 does not depend onthe output of the NS 11 but is made to output repeatedly the signals of0-9 in turn in the A/D conversion apparatus of FIG. 19, FIG. 24 is theblock diagram representing an example of the conventional D/A conversionapparatus, FIG. 25 is the block diagram representing one example of thenoise shaper 11 of FIG. 24, FIG. 26 is the output signal spectrum of theD/A conversion apparatus of FIG. 24, FIG. 27 is the block diagramrepresenting an example of the conventional A/D conversion apparatus,FIG. 28 is the output signal spectrum of the A/D conversion apparatus ofFIG. 27, FIG. 29 is the output signal spectrum of the A/D conversionapparatus of FIG. 27 based on Table 2.

DETAILED DESCRIPTION OF THE INVENTION

Hereafter, embodiments of the present invention are elucidated withreference to figures.

FIG. 1 is a block diagram representing an embodiment of the D/Aconversion apparatus in accordance with the present invention. In FIG.1, numeral 10 designates a digital filter (DF), numeral 11 designates anoise shaper (NS), and both have the same configuration & function asthose shown in FIG. 24. Numeral 12 designates a decoder (DEC), and 1-bitsignals of the number of m are output in correspondence to the digitalsignal which is output from the NS 11. Numeral 13 designates a 1-bit D/Aconverter array (DAC), which is comprised of uniform m number of 1-bitD/A converters from a first D/A converter (DAC-1) to an m-th D/Aconverter (DAC-m). Numeral 14 designates an analog adder, whichtotalizes analog signals of the number of which are output from the DAC13 and outputs as an analog signal. Numeral 15 designates a D/Aconversion circuit, which is comprised of the DAC 13 and the analogadder 14. The D/A conversion apparatus of FIG. 1, after making a digitalinput signal to the sampling frequency of 64 fs, the level of 11 (=p) bythe DF 11 and the NS 11, it is made into bit signal of the number of mby the DEC 12 and moreover is converted to an analog signal by the D/Aconversion circuit 15; and it is formed the D/A converter of so-calledoversampling type which converts the digital signal to the analog signalwith a higher sampling frequency.

An example of the D/A conversion circuit 15 of FIG. 1 is shown in FIG.2. In FIG. 2, numeral 13 designates a 1-bit D/A converter array (DEC),numeral 14 designates an analog adder, numeral 15 designates a D/Aconversion circuit, and each corresponds to FIG. 1. Numeral 20 is aninverter, and which outputs by inverting a 1-bit input signal. Numerals21, 22 designate resistors, numeral 23 designates an operationalamplifier (operational amplifier). Operation of FIG. 2 is elucidated,first, a non-invert input terminal of the operational amplifier 23 isgrounded, and an invert input terminal is made to a virtual groundpoint. Moreover, all of the 1-bit input signals are connected to theinvert input terminal of the operational amplifier 23 through theresistor 22. Namely, a current adding circuit by the resistors 21, 22 isformed. It is now assumed that the resistance value of the resistor 21of the DAC-1 is R1, the resistance value of the resistor 21 of the DAC-2is R2, . . . , the resistance value of the resistor 21 of the DAC-m isRm and the resistance value of the resistor 22 is Rf, an analog outputvoltage Eo is derived by equation (6): ##EQU2## where, V: inverteroutput voltage,

Si: inverter output logic (i=1, 2, . . . , m), ##STR1##

Here, since all of the DAC 13 have uniform configuration, the resistancevalue of the resistor 21 is also R1=R2=. . . =Rm, and the output of theoperational amplifier 23 namely the analog output is made to output avoltage value which is in proportion to the number of signal which is"0" (namely the output of the inverter 20 is "1") in the 1-bit inputsignals.

In an actual circuit, it is impossible to make the resistor 21 of theDAC 13 with perfect uniformity, and some relative error exists. In thiscase as being apparent from the equation (6), a voltage value dependingon a position as well as the number of signal which is "0" in the 1-bitinput signals is output.

An example of the DEC 12 of FIG. 1 is shown in FIG. 3. In FIG. 3,numeral 30 designates a pointer, which outputs a remnant of anaccumulation value of the input signal. Numeral 31 designates a ROM(read only memory), which outputs data of m bits corresponding to theaddress in which the input signal is a lower digit and the output of thepointer 30 is an upper digit. It is here assumed that m=10 (p-1).Operation of FIG. 3 is elucidated, first, the pointer 30 accumulates thesignals (0-10) of 11 levels output from the NS 11 of FIG. 1, and theremnant of 10 is derived and is output. Therefore, the above-mentionedoutputs become 10 ways of 0-9. Subsequently, an address in which theinput signal is a lower digit and the output signal of the pointer 30 isan upper digit is inputted to the ROM 31, and the data of 10 bits isobtained. The data of 10 bits represent 10 of 1-bit signal. Relationbetween the address (the upper digit and the lower digit are representedby respective decimal numbers) and data (10 of 1-bit signal) is shown inTable 3.

                  TABLE 3                                                         ______________________________________                                        Lower digit = 0                                                                           Lower digit = 1                                                                             Lower digit = 2                                     Upper           Upper           Upper                                         digit Data      digit   Data    digit Data                                    ______________________________________                                        0     0000000000                                                                              0       0000000001                                                                            0     0000000011                              1     0000000000                                                                              1       0000000010                                                                            1     0000000110                              2     0000000000                                                                              2       0000000100                                                                            2     0000001100                              3     0000000000                                                                              3       0000001000                                                                            3     0000011000                              4     0000000000                                                                              4       0000010000                                                                            4     0000110000                              5     0000000000                                                                              5       0000100000                                                                            5     0001100000                              6     0000000000                                                                              6       0001000000                                                                            6     0011000000                              7     0000000000                                                                              7       0010000000                                                                            7     0110000000                              8     0000000000                                                                              8       0100000000                                                                            8     1100000000                              9     0000000000                                                                              9       1000000000                                                                            9     1000000001                              ______________________________________                                        Lower digit = 3                                                                           Lower digit = 4                                                                             Lower digit = 5                                     Upper           Upper           Upper                                         digit Data      digit   Data    digit Data                                    ______________________________________                                        0     0000000111                                                                              0       0000001111                                                                            0     0000011111                              1     0000001110                                                                              1       0000011110                                                                            1     0000111110                              2     0000011100                                                                              2       0000111100                                                                            2     0001111100                              3     0000111000                                                                              3       0001111000                                                                            3     0011111000                              4     0001110000                                                                              4       0011110000                                                                            4     0111110000                              5     0011100000                                                                              5       0111100000                                                                            5     1111100000                              6     0111000000                                                                              6       1111000000                                                                            6     1111000001                              7     1110000000                                                                              7       1110000001                                                                            7     1110000011                              8     1100000001                                                                              8       1100000011                                                                            8     1100000111                              9     1000000011                                                                              9       1000000111                                                                            9     1000001111                              ______________________________________                                        Lower digit = 6                                                                           Lower digit = 7                                                                             Lower digit = 8                                     Upper           Upper           Upper                                         digit Data      digit   Data    digit Data                                    ______________________________________                                        0     0000111111                                                                              0       0001111111                                                                            0     0011111111                              1     0001111110                                                                              1       0011111110                                                                            1     0111111110                              2     0011111100                                                                              2       0111111100                                                                            2     1111111100                              3     0111111000                                                                              3       1111111000                                                                            3     1111111001                              4     1111110000                                                                              4       1111110001                                                                            4     1111110011                              5     1111100001                                                                              5       1111100011                                                                            5     1111100111                              6     1111000011                                                                              6       1111000111                                                                            6     1111001111                              7     1110000111                                                                              7       1110001111                                                                            7     1110011111                              8     1100001111                                                                              8       1100011111                                                                            8     1100111111                              9     1000011111                                                                              9       1000111111                                                                            9     1001111111                              ______________________________________                                                  Lower digit = 9  Lower digit = 10                                             Upper            Upper                                                        digit Data       digit   Data                                       ______________________________________                                                  0     0111111111 0       1111111111                                           1     1111111110 1       1111111111                                           2     1111111101 2       1111111111                                           3     1111111011 3       1111111111                                           4     1111110111 4       1111111111                                           5     1111101111 5       1111111111                                           6     1111011111 6       1111111111                                           7     1110111111 7       1111111111                                           8     1101111111 8       1111111111                                           9     1011111111 9       1111111111                                 ______________________________________                                    

The Table 3 is elucidated: the data of 10 bits is "1" only shown by thevalue of the address lower digit namely the input signal, and a sumtotal of each bit is made to be equal to the input signal. Moreover, itis shifted to the left as merely shown by the value of the address lowerdigit namely the output signal of the pointer 30, and an overfloweddigit circulates so as to appear from the right. By defining the ROM 31as shown in the Table 3, for example, the data is output as shown inTable 4.

                  TABLE 4                                                         ______________________________________                                                Input     Pointer 30 output                                                   Lower digit                                                                             Upper digit    ROM 31 output                                Time    address   address        (Data)                                       ______________________________________                                        1       5         0              0000011111                                   2       3         5              0011100000                                   3       1         8              0100000000                                   4       4         9              1000000111                                   5       8         3              1111111001                                   6       7         1              0011111110                                   7       2         8              1100000000                                   8       6         0              0000111111                                   9       10        6              1111111111                                   10      9         6              1111011111                                   11      0         5              0000000000                                   12      3         5              0011100000                                   .       .         .              .                                            .       .         .              .                                            .       .         .              .                                            ______________________________________                                    

As is understood from the Table 4, "1" as merely shown by the value ofthe input signal is output so as to circulate in the data of 10 bits,and this shows that there is no correlation between the value of theinput signal and a particular bit in the 10 bit data. For this reason,in the case that a relative error exists between the outputs of the1-bit D/A converter array 13 to which 10 bit data are connectedrespectively, generation of distortion or noise in the signal band canbe reduced.

In the D/A conversion apparatus of FIG. 1, as to the case that theoutputs of the 1-bit D/A converter array 13 have 1% of relative error(the error uniformly distributes in the range of ±1%) as shown in theTable 5, for example, result derived by simulation on output spectrum inthe same condition as FIG. 26 is shown in FIG. 4. For simplicity, where,the signals until 0-2 fs are shown.

                  TABLE 5                                                         ______________________________________                                        Position of 1-bit                                                                       Output value of 1-bit                                               D/A converter                                                                           D/A converter    Relative error [%]                                 ______________________________________                                        DAC-1     1.009            0.9                                                DAC-2     1.007            0.7                                                DAC-3     1.005            0.5                                                DAC-4     1.003            0.3                                                DAC-5     1.001            0.1                                                DAC-6     0.999            -0.1                                               DAC-7     0.997            -0.3                                               DAC-8     0.995            -0.5                                               DAC-9     0.993            -0.7                                                DAC-10   0.991            -0.9                                               ______________________________________                                    

As shown in FIG. 26, a dynamic range of 120 dB or more is obtained inthe signal band of 0-fs/2 in the output from the NS 11, but the dynamicrange is about 103 dB in FIG. 4, and it is found that deterioration ofperformance is slight in spite of existence of the relative error (adifference from average) reaching to 1% in the outputs of the 1-bit D/Aconverter array 13. On the contrary, in the case of the output in whichthe data does not circulate, for example, result derived by simulationon output signal spectrum in the case that the output of the pointer 30does not depend on the input but is fixed to 0 is shown in FIG. 5. Asseen in FIG. 5, it is recognized that noise increases in comparison withFIG. 4, and harmonic distortion is generated, and moreover the dynamicrange is severely deteriorated such as about 58 dB.

Moreover, though it is here assumed that operation of the pointer 30 isto accumulate the signals (0-10) of 11 levels output from the NS 11 ofFIG. 1 and to derive the remnant and output it, as other embodiment ofthe present invention, the operation of the pointer 30 does not dependon the output of the NS 11 but may be output repeatedly the signals of0-9 in order. Result derived by simulation on output signal spectrum inthis case is shown in FIG. 6. As seen in FIG. 6, though increases ofnoise is present in comparison with FIG. 26 or FIG. 4, the harmonicdistortion generated in the case of FIG. 5 is not found, and moreoverthe dynamic range is improved in comparison with FIG. 5. Particularly inthis method, the operation of the pointer 30 is limited outputrepeatedly the signals of 0-9 in order and a circuit scale of thepointer 30 may be reduced because accumulation and calculation of aremnant are not necessitated.

Subsequently, other embodiment of the present invention is elucidated.

Relation between an analog output in the D/A conversion circuit 15 ofFIG. 2 and a relative error of the 1-bit D/A converter array (DAC 13) iselucidated. It is now assumed that the output of the DAC-1 is D1, theoutput of the DAC-2 is D2, . . . , the output of the DAC-m is Dm and anaverage output of each DAC is D, the relative error εi (i=1, 2, . . . ,m) of each DAC has the relation of an equation (7):

    ε=Di-D

    ε1+ε2+. . . +εm=0                  (7).

It is assumed that a probability of which the number of signal being "1"in the output of the DEC 12 of FIG. 1 is 1 is P1, a probability becoming2 is P2, . . . a probability becoming m is Pm, an effective value εrmsof the relative error included in the analog output becomes an equation(8): ##EQU3##

In the equation (8), a first term of the right side depends on therelative error of each DAC, and in order to decrease this term therelative error between each DAC must be decreased. However, the secondterm and thereafter of the right side is an error which is generated bythe relative error between the DACs combined when the DAC of the numbercorresponding to the output of the DEC 12 is combined and output, andthis term can be reduced by combination of the DACs. As is apparent fromthe equation (4), in order to decrease on and after the second term ofthe right side, the sum of the relative error of neighboring DACs ispreferably decreased, and"for the purpose, it may be arranged so thatthe DAC having a relative error (a negative relative error with respectto a positive relative error, or the reverse thereof), which is contraryto the neighboring bits of the output signal array of the DEC 12, isallotted.

In the D/A conversion apparatus of FIG. 1, in the case that the outputof the 1-bit D/A converter array 13 has 1% of relative error as shown inTable 6, for example, and in the case that the code of the relativeerror is contrary in the neighboring DACs (plus and minus arealternated), result derived by simulation on output signal spectrum inthe same condition as FIG. 4 is shown in FIG. 7.

                  TABLE 6                                                         ______________________________________                                        Position of 1-bit                                                                       Output value of 1-bit                                               D/A converter                                                                           D/A converter    Relative error [%]                                 ______________________________________                                        DAC-1     1.009            0.9                                                DAC-2     0.993            -0.7                                               DAC-3     1.005            0.5                                                DAC-4     0.997            -0.3                                               DAC-5     1.001            0.1                                                DAC-6     0.999            -0.1                                               DAC-7     1.003            0.3                                                DAC-8     0.995            -0.5                                               DAC-9     1.007            0.7                                                 DAC-10   0.991            -0.9                                               ______________________________________                                    

As shown in FIG. 7, a dynamic range of 105 dB or more is obtained in thesignal band of 0-fs/2, improvement of 2 dB or more than about 103 dB ofdynamic range of FIG. 4 is understood.

Well, in the case of a general signal using 0-fs/2 as a signal band inthe oversampling, the probability Pi (i=0, 1, . . . , 9) in the equation(8) becomes the largest at P5 namely at the vicinity of the center pointof the output voltage. Namely, the arrangement for making the term ofthe P5 minimum can make maximum the dynamic range. For this purpose,now, when each 1-bit D/A converter of the DAC 13 are

D1, D2, D3, D4, . . . , Dm-3, Dm-2, Dm-1 and Dm, in the order of theoutput levels, respectively, allotment of the 1-bit D/A converter may bearranged with respect to each bit of the output signal array of the DAC12 in the order of

D1, Dm-1, D3, Dm-3, . . . , D4, Dm-2, D2 and Dm. The output of the 1-bitD/A converter array 13 becomes as shown in Table 6 by complying withthis arrangement.

Subsequently, further other embodiment of the present invention iselucidated.

FIG. 8 is a block diagram representing an embodiment of the D/Aconversion apparatus in accordance with the present invention.

In FIG. 8, numeral 10 designates the digital filter (DF), which has thesame configuration & function as those shown in FIG. 1. Numeral 41designates a noise shaper (NS) of a multi-stage quantization type, andwhich has similar configuration to the NS 11 of FIG. 25, and is made todirectly output the outputs Y1 and Y2' without addition as describedhereinafter. Numerals 42, 43 designate decoders (DEC), and the DEC 42outputs 1-bit signals of the number of m and the DEC 43 outputs 1-bitsignals of the number of n in correspondence to the digital signaloutput from the NS 41, respectively. Numerals 44, 45 designate the 1-bitD/A converter group (DAC) in a series of the 1-bit D/A converter array;and all of these are composed of uniform 1-bit D/A converters of numberof (m+n), from a first D/A converter (DAC-1) to a m-th D/A converter(DAC-m) for numeral 44, and from a first D/A converter (DAC-1) to ann-th D/A converter (DAC-n) for numeral 45. Numeral 46 designates ananalog adder, and which totalizes analog signals of the number of (m+n)output from the DAC 44 and DAC 45, and output as an analog signal.Numeral 47 designates a D/A conversion circuit, and which are composedof the DACs 44, 45 and the analog adder 46. The D/A conversion apparatusof FIG. 8 is the one which, after making the digital input signal to asampling frequency 64 fs, a signal Y1 of 7 (=p1) levels and a signal Y2'of 5 (=p2) levels by the DF 10 and the NS 41, makes the digital inputsignal into 1-bit signals of the number of m and the number of n by theDACs 42, 43, respectively, and further converts them to an analog signalby the D/A conversion circuit 47; and the apparatus is made a D/Aconversion apparatus of so called oversampling type by which a digitalsignal is converted into an analog signal by a higher samplingfrequency.

Further detailed configuration of the NS 41 of FIG. 8 is shown in FIG.9. As described above, the NS 41 of FIG. 8 has a similar configuration &function to the NS 11 of FIG. 25, and since the first order ΔΣ modulator50, the second order ΔΣ modulator 51 and the differentiator 52 are thesame ones, the elucidation is omitted. As a different point, in the NS11 of FIG. 25, though the output Y1 of the first order ΔΣ modulator 50and the output Y2' of the differentiator 52 are added by the adder 53and to output, in the NS 41 of FIG. 9, the Y1 and the Y2' are outputindependently, respectively, as described hereafter the Y1 and Y2' aremade to add by the D/A conversion circuit 47. Therefore, the adder 53may be omitted in this method, and the circuit scale may be reduced.Incidentally, the output Y1 at this time has the output (-3-+3) of 7(=p1) levels, and the output Y2' has the output (-2-+2) of 5 (=p2)levels.

An example of the D/A conversion circuit 47 of FIG. 8 is shown in FIG.10. In FIG. 10, numerals 44, 45 designate the 1-bit D/A converter group(DAC), numeral 46 designates the analog adder, which correspond to FIG.8, respectively. Numeral 60 designates an inverter, which outputs the1-bit input signal by inverting. Numerals 61, 62 designates resistors,numeral 63 designates an operational amplifier (operational amplifier).Operation of FIG. 10 is elucidated, first, the non-invert input terminalof the operational amplifier 63 is grounded, and the invert inputterminal is a virtual grand point. Moreover, all of the 1-bit inputsignals are connected to the invert input terminal of the operationalamplifier 63 through the inverters 60, the resistors 61, and moreover,is connected to the output terminal of the operational amplifier 63through the resistor 62. Namely, a current addition circuit consistingof the resistors 61, 62 is formed. it is now assumed that a resistancevalue of the resistor 61 of the DAC-1 of the DAC 44 is R11, a resistancevalue of the resistor 61 of the DAC-2 is R12, . . . , a resistance valueof the resistor 61 of the DAC-m is R1m, and a resistance value of theresistor 61 of the DAC-1 of the DAC 45 is R21, a resistance value of theresistor 61 of the DAC-2 is R22, . . . , a resistance value of theresistor 61 of the DAC-n is R2n, and a resistance value of the resistor62 is Rf, an analog output voltage Eo is derived by equation (9):##EQU4## where, V: inverter output voltage

Sij: inverter output logic (i=1, j=1, 2, . . . , m) or (i=2, j=1, 2, . .. , n) ##STR2## Here, since all of the DACs 44, 45 have uniformconfiguration, the resistance value of the resistor 61 is also

    R11=R12=. . . =R1m=R21=R22=. . . R2n,

and the output of the operational amplifier 63, namely the analogoutput, is rendered the one to output a voltage value proportional tothe number of the signals which are "0" (namely the output of theinverter 30 is "1") among the 1-bit input signals.

In an actual circuit, it is impossible to fabricate completely uniformresistor 61 of the DACs 44 and 45, and some relative error exists. Inthis case, as is obvious from the equation (9), a voltage valuedepending on a position as well as the number of the signals which are"0" in the 1-bit input signals is output.

Since the configuration operation of the DECs 42, 43 of FIG. 8 aresimilar to the DEC 12 of FIG. 1, elucidation is made by using FIG. 3 asa block diagram. In FIG. 3, numeral 30 designates the pointer, and aremnant of the accumulation value of the input signal is output. Numeral31 designates a ROM (read,only memory), which outputs data of m-bits orn-bits corresponding to an address in which the input signal is made tolower digit, and the output of the pointer 30 is made to an upper digit.It is here assumed that m=6 (=p1-1), n=4 (=p2-1). Difference of the DECs42 and 43 depends on the difference of m and n, where only the DEC 42 iselucidated because principle of operation is fundamentally identical.Incidentally, though the DEC 42 has input signals Y1 (-3-+3) of 7levels, for simplicity the elucidation is made by adding 3 to the signalto render (0-6).

Operation of FIG. 3 is elucidated, first the pointer 30 accumulates thesignals Y1 (0-6) of 7 levels output from the NS 41 of FIG. 8, andderives a remnant of 6 and outputs. Therefore, the above-mentionedoutput becomes 6 ways (0-5). Subsequently, an address, in which theinput signal is made to the lower digit and the output signal of thepointer 30 is made to the upper digit, is inputted to the ROM 31; andthe data of 6 bits is obtained. This data of 6 bits represents 6 1-bitsignals. Relation of the address (decimal number) and the data (6 1-bitsignals) at this time is shown in Table 7.

The Table 7 is elucidated; the 6-bit data is made to "1" by the extentshown by the address lower digit namely the value of the input signal;and the sum total of each bit is rendered equal to the input signal.Moreover, shifting to the left is made by the extent shown by theaddress lower digit namely the value of the output signal of the pointer30, and circulates so that overflowed digit appears from the right. Bydefining the ROM 31 as in Table 7, for example, the data is output as inTable 8.

                  TABLE 7                                                         ______________________________________                                        Lower digit = 0   Lower digit = 1 Lower digit = 2                             Upper             Upper           Upper                                       digit   Data      digit   Data    digit Data                                  ______________________________________                                        0       000000    0       000001  0     000011                                1       000000    1       000010  1     000110                                2       000000    2       000100  2     001100                                3       000000    3       001000  3     011000                                4       000000    4       010000  4     110000                                5       000000    5       100000  5     100001                                ______________________________________                                        Lower digit = 3   Lower digit = 4 Lower digit = 5                             Upper             Upper           Upper                                       digit   Data      digit   Data    digit Data                                  ______________________________________                                        0       000111    0       001111  0     011111                                1       001110    1       011110  1     111110                                2       011100    2       111100  2     111101                                3       111000    3       111001  3     111011                                4       110001    4       110011  4     110111                                5       100011    5       100111  5     101111                                ______________________________________                                                              Lower digit = 6                                                               Upper                                                                         digit Data                                              ______________________________________                                                              0     111111                                                                  1     111111                                                                  2     111111                                                                  3     111111                                                                  4     111111                                                                  5     111111                                            ______________________________________                                    

                  TABLE 8                                                         ______________________________________                                                Input     Pointer 30 output                                                   Lower digit                                                                             Upper digit    ROM 31 output                                Time    address   address        (Data)                                       ______________________________________                                        1       5         0              011111                                       2       3         5              100011                                       3       1         2              000100                                       4       4         3              111001                                       5       2         1              000110                                       6       0         3              000000                                       7       2         3              011000                                       8       5         5              101111                                       9       1         4              010000                                       10      6         5              111111                                       11      2         5              100001                                       .       .         .              .                                            .       .         .              .                                            .       .         .              .                                            ______________________________________                                    

As is understood from Table 8, "1" by the extent shown by the value ofthe input signal is output so as to circulate the 6-bit data, and thisshows that correlation of the value of the input signal and a particularbit in the 6-bit data is absent. For this reason, even in the case thata relative error exist between the outputs of the respective 1-bit D/Aconverters of the DACs 44 to which the 6-bit data are connected,respectively, generation of distortion or noise in the signal band canbe reduced.

As mentioned above, though the DEC 42 is elucidated, the DEC 43 isbasically identical thereto when the difference by which the input Y2'is 5 levels (-2-+2) and the output is 4 bits is considered.

In the D/A conversion apparatus of FIG. 8, FIG. 1l shows result derivedby simulation on output signal spectrum in the case that the samplingfrequency (FS) is 64 fs, the input signal frequency is about 0.02 fs,the input signal level is 0 dB, and the outputs of the DACs 14, 15 havethe relative error (the error distributes uniformly in the range of ±1%)of 1% as shown in Table 9, for example.

                  TABLE 9                                                         ______________________________________                                        Position of 1-bit                                                                        Output value of 1-                                                 D/A converter                                                                            D/A converter  Relative error [%]                                  ______________________________________                                        DAC 14 DAC-1   1.009          0.9                                                    DAC-2   1.007          0.7                                                    DAC-3   1.005          0.5                                                    DAC-4   1.003          0.3                                                    DAC-5   1.001          0.1                                                    DAC-6   0.999          0.1                                             DAC 15 DAC-1   0.997          -0.3                                                   DAC-2   0.995          -0.5                                                   DAC-3   0.993          -0.7                                                   DAC-4   0.991          -0.9                                            ______________________________________                                    

As shown in FIG. 26, though the dynamic range of 120 dB or more isobtained in the signal band of 0-fs/2 in the output from the NS 1, inFIG. 1l the dynamic range is about 104 dB; and it is understood that thedeterioration of performance is small in spite of presence of therelative error reaching 1% in the outputs of the DACs 44, 45.

Incidentally, if each 1-bit D/A converter of the 1-bit D/A converterarray composed of the DACs 44, 45 are arranged in the order of theoutput level and allotment is made in the order of the DACs, 44, 45 asthe Table 9 for example, the relative error of the 1-bit D/A convertergroup in each DAC may be equivalently reduced, and generation of thenoise may be reduced. Namely, in the case of Table 9 for example, thoughthe relative error totalized the DACs 44, 45 is 1%, the relative erroris 0.6% only with the DAC 44, and is 0.4% only with the DAC 45.

Moreover, in the case that the NS 41 of FIG. 8 is two stageconfiguration as shown in FIG. 9, if arrangement of the DACs 44, 45 isinverted with each other the order of the output level of each 1-bit D/Aconverter as in Table 10, generation of the above-mentioned noise isfurther may be reduced, because the probability of making the phases ofthe noises by the relative error of the 1-bit D/A converter group ineach DAC mutually inverse increases and the case canceling with eachother increases.

                  TABLE 10                                                        ______________________________________                                        Position of 1-bit                                                                        Output value of 1-bit                                              D/A converter                                                                            D/A converter  Relative error [%]                                  ______________________________________                                        DAC 14 DAC-1   1.009          0.9                                                    DAC-2   1.007          0.7                                                    DAC-3   1.005          0.5                                                    DAC-4   1.003          0.3                                                    DAC-5   1.001          0.1                                                    DAC-6   0.999          -0.1                                            DAC 15 DAC-1   0.991          -0.9                                                   DAC-2   0.993          -0.7                                                   DAC-3   0.995          -0.5                                                   DAC-4   0.997          -0.3                                            ______________________________________                                    

In the D/A conversion apparatus of FIG. 8, result derived by simulationon output signal spectrum in the case that the sampling frequency (FS)is 64 fs, the input signal frequency is about 0.02 fs, the input signallevel is 0 dB and the outputs of the DACs 44, 45 are shown in Table 10is shown in FIG. 12. As shown in FIG. 12, the dynamic range is about 105dB, and the noise is lower than the case of FIG. 1l by about 1 dB.

Moreover, if each 1-bit D/A converter of the 1-bit D/A converter arraycomposed of the DACs 44, 45 is arranged in the order of the outputlevel, and the DAC 44 is allotted to both end parts and the DAC 45 isallotted to the center part as in Table 1 for example, the difference ofan average output level of each DAC may be decreased, and because cancelof the term of Vq1 in the equation (2) and the equation (4) by additionof the outputs Y1 and Y2' of the NS 41 is accurately realized,generation of the noise may be decreased.

                  TABLE 11                                                        ______________________________________                                        Position of 1-bit                                                                        Output value of 1-bit                                                                        Difference from                                     D/A converter                                                                            D/A converter  average (error) [%]                                 ______________________________________                                        DAC 14 DAC-1   1.009          0.9                                                    DAC-2   1.007          0.7                                                    DAC-3   1.005          0.5                                                    DAC-4   0.995          -0.5                                                   DAC-5   0.993          -0.7                                                   DAC-6   0.991          -0.9                                            DAC 15 DAC-1   0.997          0.3                                                    DAC-2   0.999          0.1                                                    DAC-3   1.001          -0.1                                                   DAC-4   1.003          -0.3                                            ______________________________________                                    

In the D/A conversion apparatus of FIG. 8, result derived by simulationon output signal spectrum in the case that the sampling frequency (FS)is 64 fs, the input signal frequency is about 0.02 fs, and the inputsignal level is 0 dB and the outputs of the DACs 44, 45 are made asshown in Table 11 is shown in FIG. 13. As shown in FIG. 13, the dynamicrange is about 106 dB, and the noise is lower than the case of FIG. 1lby about 2 dB.

Moreover, in this case, in the case that the NS 11 is the two stageconfiguration as shown in FIG. 9, if the arrangement of the DACs 44, 45is made inverse with each other in the order of the output level of each1-bit D/A converter as shown in the Table 12, generation of noise may bereduced in a similar manner.

In the D/A conversion apparatus of FIG. 8, result derived by simulationon output signal spectrum in the case that the sampling frequency (FS)is 64 fs, the input signal frequency is about 0.02 fs, the input signallevel is 0 dB and the outputs of the DACs 44, 45 are made as shown inTable 12 is shown in FIG. 14. As shown in FIG. 14, the dynamic range isabout 106 dB, and the noise is lower than the case of FIG. 11 by about 2dB.

                  TABLE 12                                                        ______________________________________                                        Position of 1-bit                                                                        Output value of 1-bit                                                                        Difference from                                     D/A converter                                                                            D/A converter  average (error) [%]                                 ______________________________________                                        DAC 14 DAC-1   1.009          0.9                                                    DAC-2   1.007          0.7                                                    DAC-3   1.005          0.5                                                    DAC-4   0.995          -0.5                                                   DAC-5   0.993          -0.7                                                   DAC-6   0.991          -0.9                                            DAC 15 DAC-1   0.997          -0.3                                                   DAC-2   0.999          -0.1                                                   DAC-3   1.001          0.1                                                    DAC-4   1.003          0.3                                             ______________________________________                                    

The D/A conversion apparatus is configurated as described above.Although the NS 11 and the NS 41 represented by the equation (1) areused here, it is of cause that one functioning as the noise shaper isusable even if it has a different order or characteristic. Moreover, theconfiguration of the DAC 12 shown in FIG. 3 or the ROM data or the likeof the Table 1 is an example for description, and of cause it is notlimited to this. Moreover, although it is described in the case that theoutput bit number of m of the DEC 12 (namely the number of m of 1-bitD/A converter 13) are (p-1) with respect to the outputs of p ways of theNS 11, respectively, m may be the number which is larger than this inaccordance with the circuit configuration or the like because these arethe minimum cases. It is similar in the output bit number of m of theDEC 42 (the number of m of the DAC 44) with respect to the output Y1 ofp1 ways of the NS 41, the output bit number of n of the DEC 43 (thenumber of n of the DAC 45).

Subsequently, further embodiment of the present invention is elucidated.

FIG. 15 is a block diagram representing an embodiment of the A/Dconversion apparatus in accordance with the present invention. In FIG.15, numeral 70 designates a subtracter, numeral 71 designates anintegrator and numeral 72 designates a quantizer, and each has the sameconfiguration & function as that shown in FIG. 27. Numeral 73 designatesthe D/A converter, and which converts the output of the quantizer 72 toanalog signal. The output of the D/A converter 73 is inputted to asubtraction terminal of the subtracter 70.

Numeral 74 designates a decoder, which outputs three (=p-1) 1-bitsignals in correspondence to the digital signal output from thequantizer 72. Numeral 75 designates an 1-bit D/A converter array, whichis comprised of three uniform (=p-1) 1-bit D/A converters from a firstD/A converter (DAC-1) to a third D/A converter (DAC-3). Numeral 76designates an analog adder, which totalizes three analog signals outputfrom the 1-bit D/A converter array 75, and outputs as an analog signal.

The A/D conversion apparatus of FIG. 15 is known as a noise shaping typeA/D converter of first order characteristic, and an output Y withrespect to an input X is represented by the equation (5) in a mannersimilar to FIG. 27.

An example of a concrete circuit of the D/A converter 73 of FIG. 15 isshown in FIG. 16. In FIG. 16, the D/A converter 73, the decoder 74, the1-bit D/A converter array 75 and the analog adder 76 correspond to FIG.15, respectively. Numeral 80 designates' an inverter, and which outputsthe 1-bit input signal by inverting. Numerals 81, 82 designateresistors, numeral 83 designates an operational amplifier (operationalamplifier). Operation of FIG. 16 is elucidated, first the noninvertinput terminal of the operational amplifier 83 is grounded, and theinvert input terminal is a virtual ground point. Moreover, all of the1-bit input signals are connected to the invert input terminal of theoperational amplifier 80 through the inverters 80, the resistors 81, andfurthermore, are connected to the output terminal of the operationalamplifier 23 (sic) through the resistor 82. Namely, a current additioncircuit is composed of the resistors 81, 82. It is now assumed that theresistance value of the resistor 81 of the DAC-1 is R1, the resistancevalue of the resistor 81 of the DAC-2 is R2, the resistance value of theresistor 81 of the DAC-3 is R3 and the resistance value of the resistor82 is Rf, an analog output voltage Eo is derived by an equation (10):##EQU5## where, V: inverter output voltage

Si: inverter output logic (i=1, 2, 3) ##STR3##

Here, since all of the 1-bit D/A converters 75 are uniformlyconfigurated, the resistance value of the resistor 81 is also R1=R2=R3,and the output of the operational amplifier 83 namely the analog outputis made to output a voltage value which is proportional to the number ofthe signal being "0" (namely the output of the inverter 20 is "1") inthe 1-bit signal output from the decoder 74.

In the actual circuit, it is impossible to fabricate the resistors 81 ofthe 1-bit D/A converter 75 with perfect uniformity, and there is somerelative error. In this case, as is apparent from the equation (10), thevoltage value which not only depend on the number of the signal being"0" of the output signals of the decoder 74 but also depends on theposition is output.

Since the configuration & operation of the DEC 74 of FIG. 15 is similarto the DEC 12 of FIG. 1, elucidation is made by using FIG. 3 as a blockdiagram. An example of the decoder 74 of FIG. 15 is shown in FIG. 3. InFIG. 3, numeral 30 designates a pointer, which outputs a remnant of anaccumulation value of the input signal. Numeral 31 designates a ROM(read only memory) which outputs data of 3 bits in correspondence to anaddress in which the input signal is a lower digit, the output of thepointer 30 is an upper digit.

Operation of FIG. 3 is elucidated; first the pointer 30 accumulates theinput signal namely the signals of 2 bits ("00"-"11") output from thequantizer 72 of FIG. 15, and derives a remnant of 3 and output.Therefore, the above-mentioned output becomes three ways of 0-2.Subsequently, an address in which the input signal is the lower digitand the output signal of the pointer 30 is an upper digit is inputted tothe ROM 31, and the data of 3 bits is obtained. The data of 3 bitsrepresents three of the 1-bit signals. Relation between the address(decimal number) and the data (binary number) is shown in Table 13.

                  TABLE 13                                                        ______________________________________                                        Lower digit = 0         Lower digit = 1                                       Upper                       Upper                                             digit      Data             digit  Data                                       ______________________________________                                        0          000              0      001                                        1          000              1      010                                        2          000              2      100                                        ______________________________________                                        Lower digit = 2         Lower digit = 3                                       Upper                       Upper                                             digit      Data             digit  Data                                       ______________________________________                                        0          011              0      111                                        1          110              1      111                                        2          101              2      111                                        ______________________________________                                    

The Table 13 is elucidated; the 3 bit data becomes "1" by the numbershown by the value of the address lower digit namely the input signal,and the sum total of each bit is made to equal to the input signal.Moreover, shifting is made to the left by the value of the address lowerdigit namely the output signal of the pointer 30, and circulation ismade so that the overflowed digit appears from the right. By definingthe ROM 31 as the Table 13, the data is output as Table 14, for example:

                  TABLE 14                                                        ______________________________________                                                Input signal                                                                             Output signal of                                                                             Output signal                                       (Lower digit                                                                             pointer 30 (Upper                                                                            of ROM 31                                   Time    of address)                                                                              digit of address)                                                                            (Date)                                      ______________________________________                                        1       0          0              000                                         2       1          0              001                                         3       1          1              010                                         4       1          2              100                                         5       3          0              111                                         6       2          0              011                                         7       1          2              100                                         8       2          0              011                                         9       2          2              101                                         .       .          .              .                                           .       .          .              .                                           .       .          .              .                                           ______________________________________                                    

As is apparent from the Table 14, "1" by the extent shown by the valueof the input signal is output so as to circulate the 3 bit data, andthis shows that there is no correlation between the value of the inputsignal and a specified bit in the 3 bit data. Therefore, in the casethat a relative error exists in the output of the 1-bit D/A converter 15to which the 3 bits data are connected respectively, generation ofdistortion or noise in the signal band may be decreased.

In the A/D conversion apparatus of FIG. 15, result derived by simulationon output signal spectrum in the case that the sampling frequency (FS)is 64 fs, the input signal frequency is about 0.02 fs, the input signallevel is 0 dB and the output of the 1-bit D/A converter array 15 has 3%of relative error as shown in Table 15 for example is shown in FIG. 17.Here, the signals until 0-2 fs are shown for simplicity.

As shown in FIG. 28, in the case that the D/A converter 13 is ideal (noerror), about 57 dB of dynamic range is obtained in the signal band of0-fs/2, but the dynamic range is approximately identical in FIG. 17, andit is understood that the similar ability is obtainable in spite ofexistence of the relative error reaching 3% in the output of the 1-bitD/A converter array 15. On the contrary, in the case of the output inwhich the data does not circulate, for example in the case that theoutput of the pointer 30 does not depend on the input but is fixed to 0,the output of the D/A converter 13 is equivalent to the Table 2, and atthis time a large harmonic distortion is generated in comparison withFIG. 17 as shown in FIG. 29, and moreover, the dynamic range is greatlydeteriorated.

                  TABLE 15                                                        ______________________________________                                        1-bit data position of                                                                        Output value of 1-bit                                         ROM 31 output signal                                                                          D/A converter                                                 ______________________________________                                        0               1.02                                                          1               0.98                                                          2               1.00                                                          ______________________________________                                    

And, although it is here assumed that operation of the pointer 30accumulates the signals ("00"-"11") of 2 bits output from the quantizer72 of FIG. 15 derives a remnant of 3 and outputs, as another embodimentof the present invention, the operation of the pointer 30 does notdepend on the output of the quantizer 72 but may be output repeatedlythe signals of 0-2 in order. Result derived by simulation of the samecondition as FIG. 17 on the output signal spectrum in this case is shownin FIG. 18. As seen in FIG. 18, although noise increases in comparisonwith FIG. 17, the harmonic distortion generated in the case of FIG. 29is not found, and moreover the dynamic range is improved to about 54 dB.Particularly, in this method, the operation of the pointer 30 is outputby the extent repeatedly the signals of 0-2 in order, and the circuitscale of the pointer 30 is reduced because accumulation and calculationof a remnant are not needed.

Subsequently, further embodiment of the present invention is elucidated.

FIG. 19 is a block diagram representing further embodiment of the A/Dconversion apparatus in accordance with the present invention. In FIG.19, numeral 70 designates the subtracter, numeral 71 designates theintegrator, numeral 72 designates the quantizer and numeral 73designates the D/A converter; and each has the same configuration &function as that shown in FIG. 15. Moreover, numeral 77 designates asubtracter, numeral 78 designates an integrator; and each has the sameconfiguration & function as the subtracter 70 or the integrator 71.

Operation of FIG. 19 is elucidated; first an analog input from outsideis inputted to an addition terminal of the subtracter 77, and an analogsignal output from the subtracter 77 is accumulated by the accumulator78 and is output, moreover, is inputted to an addition terminal of thesubtracter 70. Successively, the analog signal output from thesubtracter 70 is accumulated by the integrator 71 and is output, andabove-mentioned output is converted from the analog signal to a digitalsignal by the quantizer 72, and becomes a digital output. Moreover, thisdigital output is inputted to the D/A converter 73 too, and is convertedto an analog signal, and is inputted to subtraction terminals of thesubtracter 77 and the subtracter 70.

The A/D conversion apparatus of FIG. 19 is known as a noise shaping typeA/D converter of second order characteristic, and an output Y withrespect to an input X is represented by equation (11):

    Y=X+(1-z.sup.-1).sup.2 ·Vq                        (11)

where,

Vq: quantization error of quantizer 72,

z⁻¹ =cos θ-j·sin θ,

j: imaginary number unit.

In the A/D conversion apparatus of FIG. 19, result derived by computersimulation on the output signal spectrum in the case that the samplingfrequency (FS) is 64 fs, the input signal frequency is about 0.02 fs andthe input signal level is 0 dB is shown in FIG. 20. For simplicity,here, the band until 0-2 fs is shown. As shown in FIG. 20, about 83 dBof dynamic range (D.R.) is obtained in the signal band of 0-fs/2.

It is now assumed that the D/A converter 73 of FIG. 19 has error of 3%as shown in the Table 2 in a manner similar to the D/A converter 79 ofFIG. 27, when the output signal spectrum at this time is derived bycomputer simulation, it becomes as FIG. 21. For simplicity, here, a banduntil 0-2 fs is shown. As shown in FIG. 21, generation of large harmonicdistortion is found, and the dynamic range in the signal band of 0-fs/2is severely deteriorated to about 48 dB.

On the contrary, in the case that the D/A converter 73 is relevant tothe D/A converter 73 of FIG. 15, input-output relation of the ROM 31 ofthe decoder 74 is made as shown in Table 13, and the output of the 1-bitD/A converter array 75 has 3% of relative error as shown in Table 15,the output signal spectrum becomes as shown in FIG. 22. For simplicity,here, the signal until 0-2 fs is shown. As shown in FIG. 22, it isrecognized that the dynamic range is about 83 dB, and deterioration ofability is slight in spite of existence of 3% of relative error in theoutput of the D/A converter array 75.

Moreover, as still other embodiment of the present invention, in the D/Aconverter 73 of FIG. 19, in a similar manner to the D/A converter 73 ofFIG. 15, operation of the pointer 30 of FIG. 3 does not depend on theoutput of the quantizer 72 but may be the one to output the signals of0-2 repeatedly in order. Result derived by simulation on the outputsignal spectrum in this case is shown in FIG. 23. As is seen in FIG. 23,although the noise increases in comparison with FIG. 22, the harmonicdistortion generated in the case of FIG. 21 is not found, and moreoverthe dynamic range is improved to about 56 dB.

Even in the case that the relative error exists between the outputs ofthe 1-bit D/A converter array as this, the A/D conversion apparatus ofwhich generation of the distortion or noise in the signal band is smallis realizable. Incidentally, although the A/D conversion apparatus iselucidated herein on FIG. 15 and FIG. 19, if it has a similar function &characteristic, different configuration may be available, and forexample, an apparatus performing simultaneously operation of thesubtracter 70 and the integrator 71 may be available. Moreover, theconfiguration of the decoder 74 shown in FIG. 3 and the ROM data etc. ofthe Table 13 are each one example for elucidation, and of course notlimited to these. Moreover, although the number of output bit of thedecoder 74 (namely the number of the 1-bit D/A converter 15) iselucidated as (p-1) with respect to the output of p ways of thequantizer 72, any of these are the minimum case, and therefore a numbermore than this is available in accordance to condition of circuitconfiguration or the like.

INDUSTRIAL APPLICABILITY

As mentioned above, the D/A conversion apparatus of the presentinvention, wherein the sampling frequency in D/A conversion may be equalto sampling frequency of the digital output of the noise shaper, hassuch a superior feature that operation in a clock signal of far lowerfrequency in comparison with the PWM is available.

Moreover, since the decoder is made to allot the output of the noiseshaper so as to circulate to plural 1-bit D/A converters, there is nocorrelation between the output value of the noise shaper and a specified1-bit D/A converter; and even in the case that the relative error existsin the output between respective 1-bit D/A converters, it has such asuperior feature that generation of the distortion or the noise in thesignal band may be decreased.

Moreover, the A/D conversion apparatus of the present invention candecrease generation of distortion or noise in the signal band even inthe case that the relative error exists in the output of the 1-bit D/Aconverter in the above-mentioned D/A conversion circuit, by making theD/A conversion circuit to the D/A conversion apparatus of the presentinvention; therefore it has superior features that a precision device isnot needed for the D/A conversion circuit, it is easy in fabrication andan A/D conversion apparatus with high accuracy A/D conversion apparatuscan be realized.

Moreover, in the A/D conversion apparatus of the present invention, bymaking it the noise shaping type A/D converter of the second ordercharacteristic, the accuracy of A/D conversion may be made furtheraccurate; and furthermore in this case, effect of decreasing generationof the distortion or the noise in the signal band against the relativeerror existing in the output of the 1-bit D/A converter 15 becomesfurther remarkable. Moreover, since a lower sampling frequency may beused in order to obtain the A/D conversion accuracy similar to the firstorder noise shaping type A/D converted, the apparatus may be mnade a lowoperation speed one.

We claim:
 1. A D/A conversion apparatus for converting a digital inputsignal to an analog output signal the apparatus comprising:a digitalfilter having as an input said digital input signal, the digital filterfor multiplying a sampling frequency of said digital input signal by k(k≧2), a noise shaper having as an input an output of said digitalfilter, the noise shaper for changing a frequency characteristic ofnoise to a predetermined characteristic with a word limitation, adecoder having as an input an output of said noise shaper, forconverting the noise shaper output to a 1-bit signal array, a 1-bit D/Aconverter array comprised of a plurality of 1-bit D/A converters forconverting the 1-bit signal array output of said decoder tocorresponding analog signal outputs, and an analog adder for totalizingthe outputs of said 1-bit D/A converter array and generating said analogoutput signal therefrom.
 2. A D/A conversion apparatus comprising:adigital filter for multiplying a sampling frequency of an inputteddigital signal by k (k≧2), a multi-stage quantizing type noise shaper towhich an output of said digital filter is inputted for changing afrequency characteristic of noise to a predetermined characteristic witha word length limitation, a plurality of decoders to which outputs ofrespective stages of said noise shaper are inputted for converting eachof the noise shaper outputs to a 1-bit signal array, a 1-bit D/Aconverter array comprised of a plurality of 1-bit D/A converters forconverting respective outputs of said plurality of decoders to analogsignals, and an analog adder for totalizing the analog output signals ofsaid 1-bit D/A converter array.
 3. An A/D conversion apparatus forconverting an analog input signal to a digital output signal, theapparatus comprising:a subtracter having a subtraction terminal and anaddition terminal, to which two analog signals are inputted,respectively and from which an analog output representing a differenceof both analog signals is output, an integrator for integrating theanalog output of said subtracter, a quantizer for converting an outputof said integrator to a digital signal, a decoder for converting thedigital signal output from said quantizer to a 1-bit signal array ofoutputs corresponding to a value of said digital signal, a 1-bit D/Aconverter array comprising a plurality of 1-bit D/A converters forconverting the outputs of said decoder to respective output analogsignals, and an analog adder for totalizing the outputs of said 1-bitD/A converter array, wherein an output of said analog adder comprisesthe analog signal input to the subtraction terminal of said subtracter,the analog input signal comprises the analog signal input to theaddition terminal of said subtracter, and the digital output signalcomprises said digital signal output of said quantizer.
 4. An A/Dconversion apparatus for converting an analog input to a digital output,comprising:a first subtracter having an addition terminal and asubtraction terminal to which two analog signals are inputted and fromwhich an analog output representing a difference of both analog signalsis output, a first integrator for integrating the analog output of saidfirst subtracter and generating an analog output therefrom, a secondsubtracter having an addition terminal and a subtraction terminal,wherein the analog output of said first integrator is inputted to theaddition terminal, the second subtracter generating an analog output, asecond integrator for integrating the analog output of said secondsubtracter, a quantizer for converting an output of said secondintegrator to a digital signal, a decoder for converting the digitalsignal output of said quantizer to a 1-bit signal array, a 1-bit D/Aconverter array comprising a plurality of 1-bit D/A converters forconverting the outputs of said decoder to respective analog signals, andan analog adder for totalizing the outputs of said 1-bit D/A converterarray and outputting a signal to the subtraction terminals of said firstand second subtracters, whereinthe analog input is inputted to theaddition terminal of said first subtracter, and the digital output isoutput from said quantizer.
 5. The D/A conversion apparatus of claim 1,wherein the 1-bit signal array output of said decoder comprises at leasta 1-bit signal array of (p-1) corresponding to the noise shaper outputsignal having a value of P where P is an integer, and the 1-bit signalarray is allotted by circulating in a manner that a starting position ofallotment of said 1-bit signal array becomes a next position of a finalallotment position of said 1-bit signal array of a previous sample data.6. The D/A conversion apparatus of claim 1, whereinthe 1-bit signalarray output of said decoder comprises at least a 1-bit signal array of(p-1) corresponding to the noise shaper output signal having the valueof p, where p is an integer and a starting point of allotment of said1-bit signal array circulates by a predetermined number every 1 sampledata.
 7. The D/A conversion apparatus of claim 5, whereinthe pluralityof 1-bit D/A converters corresponding to the 1-bit signal array of saiddecoder output are arranged such that polarity of an error with anaverage output level of said 1-bit D/A converter is opposed and anabsolute value of said error is closed.
 8. The D/A conversion apparatusof claim 5, wherein the plurality of 1-bit D/A converters comprises mD/A converters, m being an integer, andwhen each 1-bit D/A converter ofm in said 1-bit D/A converter array is made to DAC-1, DAC-2, DAC-3,DAC-4, . . . , DAC-(m-3), DAC-(m-2), DAC-(m-1), DAC-m in the order ofthe output level, the 1-bit D/A converter is allotted in arrangement ofDAC-1, DAC-(m-1), DAC-3, DAC-(m-3), . . . , DAC-4, DAC-(m-2), DAC-2,DAC-m with respect to the 1-bit signal array output from said decoder.9. The D/A conversion apparatus of claim 5, wherein the plurality of1-bit D/A converters are accorded to respective group, each groupcorresponding to a respective decoder andeach group is allotted in theorder of the output level of said 1-bit D/A converter array.
 10. The D/Aconversion apparatus of claim 2, wherein the multi-stage noise shapercomprises a two stage configuration, the plurality of decoders comprisesa first decoder and a second decoder to which the outputs of said noiseshaper are inputted, respectively, and the plurality of D/A convertersare grouped into a first group and a second group, respectively, whereinthe groups corresponding to each output of said decoders allot in theorder of an output level of the 1-bit D/A converter in said 1-bit D/Aconverter array,the first group of 1-bit D/A converters is arranged ininverse order of the output level, and the second group of 1-bit D/Aconverters is arranged in the order of the output level.
 11. The D/Aconversion apparatus of claim 5, whereineach 1-bit D/A converter in said1-bit D/A converter array is allotted in an order such that the outputof said decoder is near to the center with respect to the order of theoutput level of said 1-bit D/A converter.
 12. The D/A conversionapparatus of claim 2, wherein the multi-stage noise shaper comprises atwo stage configuration, the plurality of decoders comprises a firstdecoder and a second decoder to which the outputs of said noise shaperare inputted, respectively, and the plurality of D/A converters aregrouped into a first group and a second group, respectively, whereinthegroups are made to allot both end parts to the first group with respectto the order of the output level of the 1-bit D/A converter in said1-bit D/A converter array, and to allot a central part of a remainder tothe second group, and said first group is arranged in the order of theoutput level, and said second group is arranged in inverse order of theoutput level.
 13. The D/A conversion apparatus of claim 2, wherein the1-bit signal array output of said decoders comprises at least a 1-bitsignal array of (p-1) corresponding to the noise shaper output signalshaving a value of P where P is an integer, and the 1-bit signal array isallotted by circulating in a manner that a starting position ofallotment of said 1-bit signal array becomes a next position of a finalallotment position of said 1-bit signal array of a previous sample data.14. The D/A conversion apparatus of claim 13, wherein the plurality of1-bit D/A converters corresponding to the 1-bit signal array output ofsaid decoders are arranged such that polarity of an error with anaverage output level of said 1-bit D/A converters is opposed and anabsolute value of said error is closed.
 15. The D/A conversion apparatusof claim 13, wherein the plurality of 1-bit D/A converters comprises mD/A converters, m being an integer, and when each 1-bit D/A converter ofm in said 1-bit D/A converter array is made to DAC-1, DAC-2, DAC-3,DAC-4, . . . , DAC-(m-3), DAC-(m-2), DAC-(m-1), DAC-m in the order ofthe output level, the 1-bit D/A converter is allotted in arrangement ofDAC-1, DAC-(m-1), DAC-3, DAC-(m-3), . . . , DAC-4, DAC-(m-2), DAC-2,DAC-m with respect to the 1-bit signal array output from said decoders.16. The D/A conversion apparatus of claim 13, wherein the plurality of1-bit D/A converters are accorded to respective groups, each groupcorresponding to a respective decoder and each group is allotted in theorder of the output level of said 1-bit D/A converter array.
 17. The D/Aconversion apparatus of claim 13, wherein each 1-bit D/A converter insaid 1-bit D/A converter array is allotted in an order such that theoutput of said decoders is near to the center with respect to the orderof the output level of said 1-bit D/A converter.
 18. The D/A conversionapparatus of claim 2, wherein the 1-bit signal array output of saiddecoders comprises at least a 1-bit signal array of (p-1) correspondingto the output signals of the noise shapers having the value of p, wherep is an integer, and a starting point of allotment of said 1-bit signalarray circulates by a predetermined number every 1 sample data.
 19. TheA/D conversion apparatus of claim 3, wherein the 1-bit signal arrayoutput of said decoder comprises at least a 1-bit signal array of (p-1)corresponding to the digital signal output of said quantizer having avalue of P, where P is an integer, and the 1-bit signal array isallotted by circulating in a manner that a starting position ofallotment of said 1-bit signal array becomes a next position of a finalallotment position of said 1-bit signal array of a previous sample data.20. The A/D conversion apparatus of claim 19, wherein the plurality of1-bit D/A converters corresponding to the 1-bit signal array of saiddecoder output are arranged such that polarity of an error with anaverage output level of said 1-bit D/A converter is opposed and anabsolute value of said error is closed.
 21. The A/D conversion apparatusof claim 19, wherein the plurality of 1-bit D/A converters comprises mD/A converters, m being an integer, and when each 1-bit D/A converter ofm in said 1-bit D/A converter array is made to DAC-1, DAC-2, DAC-3,DAC-4, . . . , DAC-(m-3), DAC-(m-2), DAC-(m-1), DAC-m in the order ofthe output level, the 1-bit D/A converter is allotted in arrangement ofDAC-1, DAC-(m-1), DAC-3, DAC-(m-3), ..., DAC-4, DAC-(m-2), DAC-2, DAC-mwith respect to the 1-bit signal array output from said decoder.
 22. TheA/D conversion apparatus of claim 19, wherein the plurality of 1-bit D/Aconverters are accorded to respective groups and each group is allottedin the order of the output level of said 1-bit D/A converter array. 23.The A/D conversion apparatus of claim 19, wherein each 1-bit D/Aconverter in said 1-bit D/A converter array is allotted in an order suchthat the output of said decoder is near to the center with respect tothe order of the output level of said 1-bit D/A converter.
 24. The A/Dconversion apparatus of claim 3, wherein the 1-bit signal array outputof said decoder comprises at least a 1-bit signal array of (p-1)corresponding to the quantizer output signal having the value of p,where p is an integer, and a starting point of allotment of said 1-bitsignal array circulates by a predetermined number every 1 sample data.25. The A/D conversion apparatus of claim 4, wherein the 1-bit signalarray output of said decoder comprises at least a 1-bit signal array of(p-1) corresponding to the digital signal output of said quantizerhaving a value of P, where P is an integer, and the 1-bit signal arrayis allotted by circulating in a manner that a starting position ofallotment of said 1-bit signal array becomes a next position of a finalallotment position of said 1-bit signal array of a previous sample data.26. The A/D conversion apparatus of claim 25, wherein the plurality of1-bit D/A converters corresponding to the 1-bit signal array of saiddecoder output are arranged such that polarity of an error with anaverage output level of said 1-bit D/A converter is opposed and anabsolute value of said error is closed.
 27. The A/D conversion apparatusof claim 25, wherein the plurality of 1-bit D/A converters comprises mD/A converters, m being an integer, and when each 1-bit D/A converter ofm in said 1-bit D/A converter array is made to DAC-1, DAC-2, DAC-3,DAC-4, . . . , DAC-(m-3), DAC-(m-2), DAC-(m-1), DAC-m in the order ofthe output level, the 1-bit D/A converter is allotted in arrangement ofDAC-1, DAC-(m-1), DAC-3, DAC-(m-3), . . . , DAC-4, DAC-(m-2), DAC-2,DAC-m with respect to the 1-bit signal array output from said decoder.28. The A/D conversion apparatus of claim 25, wherein the plurality of1-bit D/A converters are accorded to respective groups and each group isallotted in the order of the output level of said 1 bit D/A converterarray.
 29. The A/D conversion apparatus of claim 25, wherein each 1-bitD/A converter in said 1-bit D/A converter array is allotted in an ordersuch that the output of said decoder is near to the center with respectto the order of the output level of said 1-bit D/A converter.
 30. TheA/D conversion apparatus of claim 4, wherein the bit signal array outputof said decoder comprises at least a 1-bit signal array of (p-1)corresponding to the quantizer output signal having the value of p,where p is an integer, and a starting point of allotment of said 1-bitsignal array circulates by a predetermined number every 1 sample data.